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Electrical Characteristics
2.5.4.3
Reset Timing Tables
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
16/CLKIN
2
? CLKIN = 20 MHz
? CLKIN = 133 MHz (400 MHz core)
? CLKIN = 166 MHz (500 MHz core)
Delay from deassertion of external PORESET to deassertion of internal
1024/CLKIN
800
120
96
800
—
—
ns
ns
ns
PORESET
3
? CLKIN = 20 MHz to 166 MHz
Delay from de-assertion of internal PORESET to SPLL lock
6400/(CLKIN/RDF)
6.17
51.2
μs
? CLKIN = 20 MHz (RDF = 1)
? CLKIN = 133 MHz (RDF = 2) (400 MHz core)
? CLKIN = 166 MHz (RDF = 2) (500 MHz core)
(PLL reference
clock-division factor)
320
96
77
320
96
77
μs
μs
μs
5
Delay from SPLL to HRESET deassertion
6
? REFCLK = 40 MHz to 166 MHz
Delay from SPLL lock to SRESET deassertion
? REFCLK = 40 MHz to 166 MHz
512/REFCLK
515/REFCLK
3.08
3.10
12.8
12.88
μs
μs
7
Setup time from assertion of RSTCONF , CNFGS, DSISYNC, DSI64,
3
—
ns
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
8
Hold time from deassertion of PORESET to deassertion of RSTCONF ,
5
—
ns
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
Note:
Timings are not tested, but are guaranteed by design.
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]
PORESET
Input
PORESET
Internal
1
pins are sampled
Host programs
Reset Configuration
Word
SPLL is locked
HRESET
Output (I/O)
SRESET
1+2
2
MODCK[3–5]
3
(no external indication)
Output (I/O)
Reset configuration write
sequence during this
period.
SPLL
locking period
5
6
Figure 9. Timing Diagram for a Reset Configuration Write
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
21
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